Nowadays, the consumer electronic products are generally provided with an advanced display as a basic device. A liquid crystal display (LCD) with high resolution and colorful screen has been commonly used in the consumer electronic products, such as cellular phone, digital camera, computer monitor, or laptop PC.
A shift register is an essential part of a driving circuit in the LCD panel. The shift register is used to drive a plurality of stages of displaying circuit in the LCD panel. Hence, the quality of circuit design for the shift register determines the performance of the LCD panel. Referring to FIG. 1, a circuit diagram of a stage of shift register 10 in a conventional LCD is shown. The shift register 11 includes a pull-up section 12, a pull-down section 14, a pull-down driving section 16, and a pull-up driving section 18. The pull-up section 12 uses a transistor NT11 for receiving a clock signal CK and outputting an output signal GOUT. The transistor NT11 has a gate electrically connected to a node N3, and the node N3 is electrically connected to another transistor NT18. The transistor NT18 has a gate for receiving a clear signal CLR.
Further referring to FIG. 2, a signal waveform diagram of each node in the conventional shift register 10 is shown. The transistor NT18 is opened to release the residual charges in the node N3 through the low voltage level VSS when the clear signal CLR in a high voltage level. However, the conventional shift register enables the clear signal CLR during a blanking time (i.e. the idle time between two frame signals inputted) for releasing the residual charges of node N3. As shown in FIG. 2, the clear signal CLR is enabled between the last stage output signal GOUT(Last) and the start signal STV enabled. Thus, the clear signal CLR is needed to be provided by an external signal from an additional power source. Furthermore, the circuit performance of last stage will be degraded if the enable time of the clear signal CLR is too close to the enable time of the last output signal GOUT(Last).
Therefore, there is a need to provide a shift register which is capable of releasing the residual charges in each stage of shift register by an internal clock signal, and the clock signal is enabled during the period of inputting a frame signal, to resolve the above-mentioned problems.